1. Field of the Invention
This invention relates generally to an 8-phase Phase-Shift Keying (8 PSK) demodulator, and more specifically to an improved demodulator featuring carrier recovery, automatic gain control, and intersymbol interference control.
2. Description of the Prior Art
A multi-phase (especially more than eight) PSK system is required to feature stable, accurate carrier recovery and automatic gain control (AGC) along with simultaneous transmission band width minimization which maintains a reasonable quality of the transmitted signals.
An example of a multi-phase PSK demodulator of the Costas loop baseband processing type featuring carrier recovery is disclosed in Japanese Patent Application No. 53-156124. This type of carrier recovery circuit, however, has encountered several problems: complexity, large power consumption, cumbersome circuitry adjustments, and intersymbol interference. The intersymbol interference is caused by variations of transmission channel characteristics and transmission distortion, and is a cause of degradation of signal quality.
Before discussing the preferred embodiments of this invention, reference is first made to FIG. 1 wherein there is shown in block diagram form, the previously mentioned 8 PSK demodulator.
In FIG. 1, an intermediate frequency (IF) signal (i.e., 8-phase phase-modulated signal) is fed to two phase detectors (or demodulators) 2 and 3 via an input terminal 101 and a signal distributor 1. A voltage-controlled oscillator (VCO) 6 applies its output to the phase detectors 2 and 3 by way of a signal distributor 5. A phase shifter 4 is interposed between the signal distributor 5 and the detector 3 and shifts the phase of the signal applied to the detector by .pi./2 radians. The IF signal is coherently (or synchronously) detected by the phase detectors 2 and 3, which apply their outputs to binary decision (B.D.) circuits 10 and 13 respectively and further to an adder 8 and a subtractor 9. The adder 8 and the subtractor 9 apply their outputs to binary decision circuits 11 and 12 respectively. Note that the outputs of the adder 8 and the substractor 9 are advanced in phase by .pi./4 and 3.pi./4 compared with the output of the phase detector 2. The binary decision circuits 10, 11, 12, and 13 respectively generate binary outputs which are fed to a code converter 14. The converter 14 produces three-channel data on its three output terminals 102 through 104 in a manner well known in the art.
In order to control the output of VCO 6, the outputs of the phase detector 2, the adder 8, the subtractor 9, and the phase detector 3 are fed to full-wave rectifiers 18, 17, 16, and 15, respectively, and are full-wave rectified by the corresponding circuits. The outputs of the full-wave rectifiers 17 and 18 are added at an adder 20, while the outputs of the full-wave rectifiers 16 and 15 are added at another adder 19. The outputs of the adders 19 and 20 are then applied to a subtractor 21, the output of which is fed to a switch 22. The binary decision circuits 10 through 13 apply their outputs to an Exclusive-OR gate 23 which supplies the switch 22 with a control signal. The switch 22 controls the polarity of the signal from the subtractor 21 in response to the control signal from the Exclusive-OR gate 23. The output of the switch 22 is an automatic phase control (APC) signal which is applied through a low pass filter (LPF) 7 to the VCO 6 for controlling the output thereof. Thus, the carrier is recovered at the VCO 6.
Difficulties are encountered in the circuitry shown in FIG. 1 in that (a) each output of the full-wave rectifiers 15 through 18 is analog processed and (b) the circuit is not provided with an AGC function. More specifically, the analog processing of the outputs of the rectifiers requires careful adjustment of the output amplitudes and the DC (direct current) balances with attendant increase in adjusting work. Further, an AGC circuit should be added to the FIG. 1 arrangement, resulting in a large circuit exhibiting a large power drain. Additionally, the FIG. 1 prior art is not provided with any means for avoiding intersymbol interference and hence is unable to ensure high quality signals.